1. Field of the Invention
The invention relates in general to a memory and a 1-bit error checking method thereof, and more particularly to a memory simplifying hardware configuration and saving memory space, and a 1-bit error checking method thereof.
2. Description of the Related Art
Memory device has now been widely used in the storage of data. The completeness of data storage is essential in the design of memory. Conventionally, the above data completeness is achieved via the use of an error correction code (ECC). The error correction code is used in a data completeness checking method for detecting and correcting a 1-bit error.
Referring to FIG. 1A, a flowchart of a conventional memory 1-bit error checking method is shown. Firstly, the method begins at step 100, at least one piece of data fragment whose size is 2n bits is received, wherein n is an integer greater than or equal to 0. Next, the method proceeds to step 110, an error correction code whose size is 2n bits is generated according to the at least one piece of data fragment, wherein the error correction code is generated according to an error checking and correction algorithm (ECC algorithm). In order to avoid a 1-bit error occurring to the error correction code, the error correction code further includes an error checking and correction (ECC) parity bit and its complement. The error correction code is an overhead bit for the at least one piece of data fragment.
Then, the method proceeds to step 120, the at least one piece of data fragment and the error correction code are written in the memory. After that, the method proceeds to step 130, the at least one piece of data fragment is read from the memory and used as at least one piece of read data fragment. Next, the method proceeds to step 140, a new error correction code is generated according to the at least one piece of read data fragment by using the ECC algorithm. Then, the method proceeds to step 150, a determination as to whether the at least one piece of read data fragment is the same with the at least one piece of data fragment is made according to the error correction code and the new error correction code. Substantially, in step 150, according to the error checking and correction algorithm, an “exclusive or” operation is performed on the error correction code and the new error correction code, and if the result is 0, the at least one piece of read data fragment is determined to be the same with the at least one piece of data fragment.
If the at least one piece of read data fragment is the same with the at least one piece of data fragment, then the method proceeds to step 160, the memory determines that the read operation is correct and outputs the at least one piece of read data fragment. If the at least one piece of read data fragment is different from the at least one piece of data fragment, then the method proceeds to step 170, if the memory determines that the read operation has a 1-bit error, then the memory corrects the at least one piece of read data fragment as the at least one piece of data fragment according to the new error correction code and outputs the at least one piece of read data fragment.
Referring to FIG. 1B, a schematic diagram of the error checking and correction algorithm is shown. As shown in FIG. 1B, at least one piece of data fragment whose size is 8 bits (D0˜D7) is exemplified. The 6-bit error correction code of the at least one piece of data fragment is generated according to the ECC algorithm. The error correction code includes ECC parity bits P1, P2 and P4, and the complements P1′, P2′ and P4′. Likewise, the new error correction code also does. The equations of ECC parity bits P1, P2 and P4, and the complements P1′, P2′ and P4′ are described as below, wherein ⊕ means “exclusive or”.P4=D7⊕D6⊕D5⊕D4  (eq. 1)P2=D7⊕D6⊕D3⊕D2  (eq. 2)P1=D7⊕D5⊕D3⊕D1  (eq. 3)P4′=D3⊕D2⊕D1⊕D0  (eq. 4)P2′=D5⊕D4⊕D1⊕D0  (eq. 5)P1′=D6⊕D4⊕D2⊕D0  (eq. 6)
In step 170, if the memory determines that the read operation has a 1-bit error, that means the result of the “exclusive or” operation performed on the error correction code and the new error correction code is not all 0. The “exclusive or” result is the error location of the at least one piece of read data fragment. Then invert the error bit and the error is corrected.
According to the conventional memory error checking method, despite the ECC algorithm is able to detect and correct a 1-bit error. However, in checking the 1-bit error of a memory, the size of the error correction code is 2n bits, not only make the overhead bit to occupy too much memory space, but also make it difficult to simplify the hardware configuration of the memory.